The present invention relates to a CMOS (Complementary Metal Oxide Semiconductor) device.
If a silicon gate CMOS transistor which has a gate made of electrically conductive polycrystalline silicon is used to constitute a logic circuit, the drain of a P-channel MOS transistor must be connected to that of an N-channel MOS transistor. FIG. 1 shows an IC pattern of a CMOS inverter manufactured by a known process wherein one gate electrode is made of N-type polysilicon and the other gate electrode is made of a P-type polysilicon by using a polysilicon layer 7 which is doped with different impurities. The CMOS inverter comprises an N-type semiconductor substrate 2, a P-channel MOS transistor region 1 formed on the substrate 2, a P-type well region 4 formed in the substrate 2, an N-channel MOS transistor region formed on the P-type well region 4, and patterned polycrystalline silicon wiring layers 5, 6 and 7. The layer 6 is provided for the drains of MOS transistors, and the layer 7 for the gate electrodes thereof. An N.sup.+ -type impurity is doped in that portion of the layer 7 which lies on the P-channel transistor 1, and a P.sup.+ -type impurity is doped in that portion of the layer 7 which lies on the N-channel transistor 3. The CMOS inverter further comprises aluminum interconnection layers 8, 9 and 10. The aluminum interconnection layer 10 connects the drains of the transistors 1 and 3. Further provided are an aluminum electrode 11 used as gate of each transistor, P.sup.+ -type diffusion regions 12 and 13 used as the source and drain of the P-channel MOS transistor 1, and N.sup.+ -type diffusion regions 14 and 15 used as the source and drain of the N-channel MOS transistor 3. Further, an isolation region 16 provided, isolating the transistors 1 and 3 from each other. The aluminum interconnection layer 8 is connected to the P.sup.+ -type diffusion region 12 through a contact hole 17 made in an insulating layer interposed between the layer 8 and the region 12. Similarly, the aluminum interconnection layer 10 is connected to the P.sup.+ -type diffusion region 13 through a contact hole 18 made in the insulating layer, the aluminum layer 9 is connected to the N.sup.+ -type diffusion region 14 through a contact hole 19 made in the insulating layer. Further, the aluminum layer 10 is connected to the N.sup.+ -type diffusion region 15 through a contact hole 20 made in the insulating layer, the polycrystalline layer 7 is connected to the aluminum electrode 11 through a contact hole 21 made in the insulating layer, and the polycrystalline silicon layer 6 is connected to the aluminum layer 10 through a contact hole 22 made in the insulating layer.
FIG. 2 shows an IC pattern of a CMOS inverter utilizing a polycrystalline silicon layer which is doped with a single type of impurity, for common gates, which is manufactured by a process more advanced than the process for making the CMOS inverter of FIG. 1.
FIG. 3 is a sectional view of the CMOS inverter shown in FIG. 2, taken along line X--X' in FIG. 2. In the silicon layer 7 of the CMOS inverter shown in FIG. 1 impurities of both P.sup.+ -type and N.sup.+ -type are doped, thus forming a PN junction. To nullify the PN junction it is necessary to make a contact hole 21 in the insulating layer and thus to put the aluminum electrode 11 into contact with the PN junction. Such a contact hole is unnecessary in the CMOS inverter of FIG. 2. This is because only one impurity is doped in the silicon layer 7 of the CMOS inverter shown in FIG. 2. With such a contact hole not provided, the CMOS inverter of FIG. 2 may have a higher IC density.
In both CMOS inverters shown in FIGS. 1 and 2, however, the contact hole 22 is indispensable. Without the hole 22, the polycrystalline silicon layer 6 could not be connected to the aluminum interconnection layer 10. Either CMOS inverter is thus longer in the lateral direction than otherwise. Furthermore, the space above the region 16 isolating the transistors 1 and 3 cannot be effectively used. This is a drawback inherent to a CMOS device.